1. Field of the Invention
The present invention relates generally to semiconductor devices, and more particularly, to a semiconductor device having test pads and a pad connection unit that connects a test pad to an integrated circuit of the semiconductor device during a test operating mode.
2. Background of the Invention
Semiconductor devices, such as semiconductor memory devices, are desired to operate with higher bandwidths. Particularly, in order to improve the system operating characteristics of today's mobile memory products, an increase in the number of input/output (IO) pins that simultaneously transfer data is desired. However, increase in the number of IO pins is limited by chip size, packaging, and many other restrictions. For example, in the case of 256-bit data, 500 or more balls are required for a package ball out. However, fabricating a package with 500 or more balls is impossible in actual practice. This impracticality especially applies to cases in which a small package size is required, such as in the mobile memory device market.
A new packaging technology called micro-bump (μ-bump) is gaining prominence. Point to point access is performed between a control chip and a memory chip in a typical mobile product. Thus, μ-bump is a packaging technology that directly connects a control chip to a memory chip without the use of wires by matching the respective pads of the control and memory chips according to signals to be transferred.
However with significant size decrease in μ-bump technology, probing of pads during wafer testing may be difficult. Namely, probing small pads formed on a wafer with integrated circuit dies intended for μ-bump technology may be difficult.